Fractional-N synthesizers are a common practice in modern radio frequency (RF) transceivers desiring fine frequency resolution with high phase noise performance, typical to broadband or high data-rate applications. While a fractional-N synthesizer may operate at high frequency for a given channel spacing, it may also suffer from any non-linear effects that exist within elements of the synthesizer. This may eventually cause noise folding of the high-pass shaped noise of a delta-sigma modulator (DSM) employed in a feedback loop of the synthesizer. This noise folding may, in turn, cause a noise floor to increase and the integrated phase noise of the synthesizer to degrade.
Non-linear delay variation of a multi-modulus divider of the feedback loop may contribute to non-linearity and noise folding characteristics of these fractional-N synthesizers. One known approach for mitigating such delay variation is by re-sampling the divider output using a voltage controlled oscillator (VCO) frequency. However, this may be difficult to implement, especially at high VCO frequency, and may increase the synthesizer power-consumption.